Bypassing Multicore Memory Bugs with Coarse-Grained Reconfigurable Logic

Multicore systems deploy sophisticated memory hierarchies to improve memory operations' throughput and latency, by exploiting multiple levels of cache hierarchy and several complex memory-access instructions. As a result, the functional verification of the memory subsystem is one of the most challenging tasks in the overall system design effort, leading to many bugs escaping into the released product. In this work we propose MemPatch, a novel...