IEEE Transactions on Computers
Papers 10,000
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#1Dan HuangH-Index: 6
#2Jun WangH-Index: 118
Last. Jiangling YinH-Index: 8
view all 6 authors...
Big Data platforms recently employ resource management systems, such as YARN, Mesos, and Google Borg, to provision computational resources. These systems adopt containerization to share the computing resources in a multi-tenant setting with low performance overhead and interference. However, it may be observed that tenants often interfere with each other on the underlying Big Data File Systems (BDFS), e.g. Hadoop File System, which have been widely deployed as a persistent layer in current data ...
#1Yuanbo Wen (USTC: University of Science and Technology of China)
#2Qi Guo (CAS: Chinese Academy of Sciences)H-Index: 13
Last. Tianshi ChenH-Index: 26
view all 11 authors...
Machine Learning Computers (MLCs) with tensor functional units (e.g., NVIDIA's Tensor Core, Google's TPU and Habana's Tensor Processor Core) have emerged significantly over recent years. The broad diversity of MLCs makes it hard to deploy machine learning workloads with optimized performance. Though deep learning compilers (e.g., TVM) are effective to produce optimized code for different hardware back-ends, when deploying to a new MLC, it is tedious to implement platform-specific compilation opt...
#1Doowon Lee (UM: University of Michigan)H-Index: 3
#2Valeria Bertacco (UM: University of Michigan)H-Index: 38
Multicore systems deploy sophisticated memory hierarchies to improve memory operations' throughput and latency, by exploiting multiple levels of cache hierarchy and several complex memory-access instructions. As a result, the functional verification of the memory subsystem is one of the most challenging tasks in the overall system design effort, leading to many bugs escaping into the released product. In this work we propose MemPatch, a novel reconfigurable hardware solution to bypass such escap...
#1Biruk B. SeyoumH-Index: 2
#2Marco PaganiH-Index: 5
Last. Giorgio ButtazzoH-Index: 66
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#1Wei ZhangH-Index: 6
#2Hang ZhangH-Index: 4
Last. John Lach (UVA: University of Virginia)H-Index: 32
view all 3 authors...
#1Won Gi ChoiH-Index: 3
#2Do Young KimH-Index: 68
Last. Sanghyun ParkH-Index: 35
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The log structured merge (LSM) tree has been widely adopted by database systems owing to its superior write performance. However, LSM-tree based databases face vulnerabilities when processing analytical queries due to the read amplification caused by its architecture and the limited use of storage devices with high bandwidth. To flexibly handle transactional and analytical workloads, we proposed and implemented OurRocks taking full advantage of NVMe SSD and GPU devices, which improves scan perfo...
#2Vincent Loechner (IRIA: French Institute for Research in Computer Science and Automation)H-Index: 1
Last. Cédric Bastoul (IRIA: French Institute for Research in Computer Science and Automation)H-Index: 18
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Modern computers keep following the traditional model of addressing memory linearly for their main memory and out-of-core storage. While this model allows efficient row access to row-major 2D matrices, it introduces complexity to perform efficient column access. A common strategy to improve these accesses is to transpose or rotate the matrix beforehand, thus the accessing complexity is centralized in one transformation operation. Further column accesses are performed as row accesses to the trans...
Scalable Networks-on-Chip (NoCs) have become the standard interconnection mechanisms in large-scale multicore architectures. These NoCs consume a large fraction of the on-chip power budget, where the static portion is becoming dominant as technology scales down to sub-10nm node. Therefore, it is essential to reduce static power so as to achieve energy-efficient computing. Power-Gating, as an effective static power saving technique, can be used to power off inactive routers for static power savin...
#1Siyuan XiaoH-Index: 1
#2Xiaohang WangH-Index: 11
Last. Terrence MakH-Index: 17
view all 6 authors...
For many applications showing error forgiveness, approximate computing is a new design paradigm that trades application output accuracy for mitigating computation/communication effort, which results in performance/energy benefit. Since networks-on-chip (NoCs) are one of the major contributors to system performance and power consumption, the underlying communication is approximated to achieve time/energy improvement. However, performing approximation blindly causes unacceptable quality loss. In t...
The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This ...
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