Marketing

Process (computing)

Technology roadmap

Resist

Materials science

Layer (electronics)

Computer security

Computational lithography

Operating system

Telecommunications

Multiple patterning

Computer science

Photoresist

Business

Nanotechnology

Lithography

Enhanced Data Rates for GSM Evolution

Photolithography

Optoelectronics

Extreme ultraviolet lithography

Key (lock)

Journal of Micro/Nanopatterning Materials and Metrology

Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future. Aim: The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years. Results: Critical dimensions in logic chips are now small enough that stochastics, i.e., random variations in photon, molecules, and photoresist image forming processes, introduces random variations in sizes and stochastic-driven defects. As critical dimensions get smaller, stochastics becomes a bigger challenge. The roadmap projects that despite projected improvements in tools, photoresist, device design, and patterning processes, resist dose to print will still have to roughly triple over the next 10 years to maintain acceptable stochastics unless major process or chip design changes are made. This will raise patterning costs substantially. Other patterning options are under development but they also have challenges related to defects. Edge placement error (EPE) is also a challenge for future devices. Long-term, logic device requirements will drive stacked devices, and yield and process complexity will be key challenges. Conclusions: Logic devices will drive leading edge lithography. Improved extreme ultraviolet lithography is a leading candidate but other options are possible. Key short-term challenges are stochastics, EPE, and cost. Resist dose to print is expected to rise substantially as critical dimensions shrink unless substantial process innovation occurs. For the long term, the challenges will be yield and process complexity when logic devices switch to 3D scaling

International Roadmap for Devices and Systems lithography roadmap