Adhesive

Engineering

Daisy chain

Materials science

Three-dimensional integrated circuit

Layer (electronics)

Telecommunications

Computer science

Thermocompression bonding

Soldering

Flip chip

Physics

Nanotechnology

Wafer bonding

Wafer

Integrated circuit

Thermal

System in package

Electronic engineering

Temperature cycling

Ball grid array

Interconnection

Composite material

Die (integrated circuit)

Meteorology

Chip

Chip-scale package

Optoelectronics

Electrical engineering

The direct bond interconnect (DBI®) Ultra technology, a low-temperature die-to-wafer (D2W) and die-to-die (D2D) hybrid bond, is a platform technology to reliably achieve submicron interconnect pitches. A reliable D2W and D2D assembly with submicron pitch capability will enable widespread disaggregation and chiplet architecture innovation. DBI Ultra offers bonding throughput comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal after bonding results in solid Cu-Cu connection with no solder and no underfill. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. We have been reporting development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications over the past few years.Previously, Invensas has reported assembly results with a single daisy chain die with a direct bond interconnect layer on one or both surfaces of the die. The die has a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 8 mm x 12 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 μm with a pad diameter of either 5, 10 or 15 μm. We have achieved >95% electrical test yield and superior reliability in temperature cycling, high temperature storage and autoclave test.In this paper, we assess the high volume production readiness of the technology using a die to wafer and die to die stacking. Critical enabling factors include the CMP process for bonding surface planarization and Cu recess control, metrology tools for CMP process control and verification, and compatibility with the silicon supply chain for assembly. The singulation technology must ensure good die edge quality and surface cleanliness. The die handling includes a die-on-tape preparation process for compatibility with low cost, high volume assembly. We will also review our continuous process and bonding yield improvement. Our new test die design with TSVs allows for electrical testing of all stacked die.

Die to Wafer Stacking with Low Temperature Hybrid Bonding