Wafer dicing

Process (computing)

Engineering

Packaging industry

Wafer-level packaging

Materials science

Layer (electronics)

Etching (microfabrication)

Operating system

Fan-out

Telecommunications

Computer science

Mold

Manufacturing engineering

Die preparation

Physics

Nanotechnology

Optics

Wafer

Integrated circuit packaging

Focus (optics)

Interposer

Composite material

Wafer-scale integration

Chip

Wafer testing

Electrical engineering

Industry interest in fan-out wafer level packaging has been increasing steadily. This is partially because of the potential behind panel-based fan-out packaging, and partially because wafer level packaging may be fulfilling needs not met by interposer-based and 3D technologies. As is the case with any technology, there are variations within the fan-out wafer level packaging category. This paper will focus on two of the primary processes: RDL-first and mold-first (also called chip-first). While these process flows have many of the same activities, those activities are carried out in a different order, and there are a few key steps that will differ. Each process has unique challenges and benefits, and these will be explored and analyzed.

A cost analysis of RDL-first and mold-first fan-out wafer level packaging