Engineering

Automation

Integrated circuit layout

Floorplan

Embedded system

Computer security

Theoretical computer science

Operating system

Telecommunications

Computer science

Mechanical engineering

Reinforcement learning

Computer architecture

Graph

Integrated circuit

Artificial intelligence

Chip

Convolutional neural network

Key (lock)

Nature

Chip floorplanning is the engineering task of designing the physical                layout of a computer chip. Despite five decades of research1, chip floorplanning has                defied automation, requiring months of intense effort by physical design engineers                to produce manufacturable layouts. Here we present a                deep reinforcement learning approach to chip floorplanning. In under                six hours, our method automatically generates chip floorplans that are superior or                comparable to those produced by humans in all key metrics, including power                consumption, performance and chip area. To achieve this, we pose chip floorplanning                as a reinforcement learning problem, and develop an edge-based graph                convolutional neural network architecture capable of learning rich and transferable                representations of the chip. As a result, our method utilizes past experience to                become better and faster at solving new instances of the problem, allowing chip                design to be performed by artificial agents with more experience than any human                designer. Our method was used to design the next generation of Google’s                artificial intelligence (AI) accelerators, and has the potential to save thousands                of hours of human effort for each new generation. Finally, we believe that more                powerful AI-designed hardware will fuel advances in AI, creating a symbiotic                relationship between the two fields. Machine learning tools are used to greatly accelerate chip layout                design, by posing chip floorplanning as a reinforcement learning problem and                using neural networks to generate high-performance chip layouts.

A graph placement methodology for fast chip design