Integrated LDOs cost-effectively enable fine-grain voltage regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regulation improving both local IR-drop and transient droop response across the IP domain [1]-[3]. However, previous distributed LDOs used custom communication between a global controller and local distributed LDO controllers [1], custom communication between neighboring LDO controllers [2], and/or analog voltage sensors with associated shared VREF generation and routing [1]-[3]. This paper presents a fully synthesizable, Distributed, and scalable all-Digital LDO (D-DLDO) voltage regulator (Fig. 25.1.1) with the following salient features: (1) fast single-cycle voltage monitoring using a Digital Supply-Voltage Sensor (DSVS), (2) fast digital PID-based controller, and (3) APR-friendly and tile-able design without the need to generate or route any global or inter-LDO digital/analog signals. A test-chip is implemented with 9 DLDO units in 10nm CMOS (Fig. 25.1.7). Each DLDO unit, including its power gates (PGs), DSVS, and controller, was fully synthesized using standard library cells and industry-standard automatic placement-and-routing (APR) tools.