DC fault current limiters (FCLs) are becoming increasingly important for the prompt dc fault clearance of modular multilevel converter (MMC)-based high-voltage direct current (HVdc) grids. This paper proposes a hybrid FCL topology, in which the main current limiting circuit is composed of thyristors, capacitors, and an inductor. Detailed theoretical analysis of the current limiting processes was carried out to check the electrical stresses. The relationship between the voltage stress and the current limiting time was analyzed, and then a design method for the FCL parameters was provided. An effective method for fast bypassing the FCL inductor was proposed to reduce the energy dissipation when fault current is interrupted by a dc circuit breaker (DCCB). The dynamic performance of the proposed approach has shown that the proposed FCL can effectively limit the rate of rising of the dc fault current and reduce the energy dissipation.