Electrical engineering

Transistor

Oversampling

Bandwidth (computing)

Transconductance

CMOS

Capacitor

Operational transconductance amplifier

Integrator

Noise shaping

Noise (video)

Image (mathematics)

Spurious-free dynamic range

Operational amplifier

Engineering

Comparator

Voltage

Artificial intelligence

Amplifier

Clock rate

Electronic engineering

Computer science

Successive approximation ADC

Telecommunications

IEEE Journal of Solid-State Circuits

This paper presents a low-power and scaling-friendly noise-shaping (NS) SAR ADC. Instead of using operational transconductance amplifiers that are power hungry and scaling unfriendly, the proposed architecture uses passive switches and capacitors to perform residue integration and realizes the path gains via transistor size ratios inside a multipath dynamic comparator. The overall architecture is simple and robust. Since the noise transfer function is set by component ratios, it is insensitive to process, voltage, and temperature (PVT) variations. Besides the proposed architecture, this paper also presents two new circuit techniques. A tri-level voting scheme is proposed to reduce the comparator noise. It outperforms the majority voting technique by exploiting more information in the comparator output statistics and providing an extra decision level. A dynamic multi-phase clock generator is also proposed to guarantee non-overlapping and support an arbitrary number of phases. A prototype 9-bit NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes 143 μW at 1.1 V while operating at 8.4 MS/s. Taking advantage of the second-order NS, it achieves a peak SNDR of 78.4 dB over a bandwidth of 262 kHz at the oversampling ratio of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting