Statistics

Randomness

Exploit

NIST

Jitter

Telecommunications

Synchronous circuit

Clock signal

Mathematics

Wireless

Application-specific integrated circuit

Computer hardware

Parallel computing

Computer science

Algorithm

Random number generation

Digital clock manager

Embedded system

Throughput

Natural language processing

Computer security

Field-programmable gate array

IEEE Transactions on Circuits & Systems II Express Briefs

True random number generators (TRNGs) are fundamentals in many important security applications. Though they exploit randomness sources that are typical of the analog domain, digital-based solutions are strongly required especially when they have to be implemented on Field Programmable Gate Array (FPGA)-based digital systems. This brief describes a novel methodology to easily design a TRNG on FPGA devices. It exploits the runtime capability of the Digital Clock Manager (DCM) hardware primitives to tune the phase shift between two clock signals. The presented auto-tuning strategy automatically sets the phase difference of two clock signals in order to force on one or more flip-flops (FFs) to enter the metastability region, used as a randomness source. Moreover, a novel use of the fast carry-chain hardware primitive is proposed to further increase the randomness of the generated bits. Finally, an effective on-chip post-processing scheme that does not reduce the TRNG throughput is described. The proposed TRNG architecture has been implemented on the Xilinx Zynq XC7Z020 System on Chip (SoC). It passed all the National Institute of Standards and Technology (NIST) SP 800–22 statistical tests with a maximum throughput of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300 \times 10^{6}$ </tex-math></inline-formula> bit per second. The latter is considerably higher than the throughput of other previously published DCM-based TRNGs.

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers