Gene

Quantum mechanics

Soft error

Voltage

Engineering

Event (particle physics)

Embedded system

Node (physics)

Robustness (evolution)

Biochemistry

Computer science

Integrated circuit design

Transistor

Physics

Electronic engineering

Structural engineering

Chemistry

CMOS

Electrical engineering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

In this article, a high-performance and low-cost single-event multiple-node-upsets resilient (HLMR) latch is proposed in 55-nm CMOS technology. By using eight normal two-input Muller-C-elements (MCEs) and eight clock-gating (CG)-based two-input MCEs, a feedback loop storage module with 16 storage nodes is constructed, which makes the latch completely triple-node-upsets (TNUs) resilient. Meanwhile, through the special layout technique which guarantees the worst quadruple-node pairs as physically apart as possible, the proposed latch is completely quadruple-node-upsets (QNUs) tolerant and almost completely QNU resilient. Simulation results have validated the robustness and low cost of the proposed latch due to the use of high-speed transmission gates (TGs), CG technology, and fewer transistors. Overhead comparisons indicate that our design saves 383.53% area-power-delay product (APDP) on average and has a lower sensitivity on process, voltage and temperature (PVT) compared with other considered up-to-date multiple-node-upsets (MNUs) tolerant latches, thus providing high reliability for safety and low-cost critical applications, especially in harsh radiative environments.

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design