As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing (HPC) applications. Fan-out technology enables multi-chip integration using fine pitch and small line width copper redistribution layer (RDL) technology to interconnect different dies resulting in a flexible and cost-effective package solution. However, as the fan-out package size increases to accommodate higher I/O counts and higher bandwidth, package warpage and reliability become more challenging. The main challenges in building large size packages (&#x0131;65x65mm2) with fan-out technology are warpage, RDL integrity, and package reliability. In this paper, we discuss the reliability assessment of a 1.6X reticle size integrated fan-out multi-chip assembly on large organic substrates for networking applications. The package integrates a 7 nm ASIC die and 8 I/O chiplets with 3 layers of fine-pitch RDL interconnection. The coefficient of thermal expansion (CTE) mismatch between different materials in the package structure can cause the device to warp and induce mechanical stresses that can cause RDL cracking and other failures in the package. We will discuss package design and processing methods for improving RDL integrity to enhance overall package reliability. By using finite element stress analysis to optimize the RDL design, robust large format multi-chip fan-out packages were developed and validated through reliability testing.

Reliability Challenges of High-Density Fan-out Packaging for High-Performance Computing Applications