Electrical engineering

Nanotechnology

Transistor

Topology (electrical circuits)

Cascode

MOSFET

Gene

Breakdown voltage

Engineering

Overvoltage

High-electron-mobility transistor

Voltage

Chemistry

Materials science

Gallium nitride

Layer (electronics)

Computer science

Optoelectronics

Biochemistry

Robustness (evolution)

IEEE Transactions on Power Electronics

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and an Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , is still lacking. This article fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by avalanche in the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4–1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8–2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency dependent. At 100 kHz, the failure boundary (∼1.3 kV) is even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices show large but recoverable parametric shifts. All these failure and degradation behaviors can be explained by the buffer trapping in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.

Robustness of Cascode GaN HEMTs in Unclamped Inductive Switching