Macroeconomics

Multiplier (economics)

Voltage

Engineering

Bandwidth (computing)

Gilbert cell

Noise figure

Broadband

Telecommunications

Economics

Harmonics

Amplifier

Computer science

BiCMOS

Antenna (radio)

Balun

Transistor

Physics

Optics

W band

Topology (electrical circuits)

CMOS

Optoelectronics

Frequency multiplier

Electrical engineering

This work presents a broadband and high power D-band multiplier by 4 chain designed in a 130 nm silicon-germanium (SiGe) BiCMOS technology. A single-ended 35 GHz input signal is made differential by a Marchand balun and multiplied by 4 by means of a Gilbert cell based quadrupler. The undesired harmonics are filtered out by a double section harmonic filter and, after a D-Band Marchand balun employed for differential to single conversion, amplified using a broadband 3-stage cascode amplifier. The presented circuit achieves a 3-dB bandwidth of 60 GHz, covering the entire D-band (110 GHz to 170 GHz) with a peak saturated output power of 8 dBm. A rejection of more than 40 dB has been measured for 3 rd , 5 th , 6 th and 7th harmonics at 140 GHz. The designed circuit consumes 280 mW from a 3.3 V supply, resulting in a drain efficiency of 1.75%. The proposed solution shows a 43 % relative bandwidth, which is, to the best of the authors' knowledge, the largest among the up to now published silicon based D-band frequency multiplier by 4 chains.

A Broadband 110–170 GHz Frequency Multiplier by 4 Chain with 8 dBm Output Power in 130 nm BiCMOS