Clock signal

Computer network

Synchronous circuit

Pipeline (software)

Asynchronous system

Gene

Operating system

Distributed computing

Computer architecture

Reduced instruction set computing

Jitter

Embedded system

Asynchronous communication

Instruction set

Chemistry

Computer science

Asynchronous circuit

Static timing analysis

Computer hardware

Field-programmable gate array

Biochemistry

Synchronizer

Robustness (evolution)

Telecommunications

IEEE Transactions on Circuits & Systems II Express Briefs

Over the past decade, the design of low-power processors is a primary requirement of emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore, there has been renewed interest in asynchronous circuits for their low-power consumption and robustness. However, one of the main obstacles is the lack of commercial EDA tool support, which makes asynchronous design takes time and is not well-suited for industrial adoption. This brief proposes a new methodology for implementing asynchronous phase-decoupled click-based circuits with traditional EDA tools. To perform static timing analysis both in the control and data paths, we capture asynchronous event propagation via generated clocks. Moreover, we present an adaptive pipeline asynchronous RISC-V processor implemented on the FPGA, Xilinx ZCU102 board. The implementation result shows that the asynchronous RISC-V processor achieves a 3× dynamic power improvement against the synchronous one with a similar resource.

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method