Algorithm

Voltage

Engineering

Computer science

Capacitor

Phase noise

Physics

Electronic engineering

Voltage-controlled oscillator

Topology (electrical circuits)

Integrator

CMOS

Electrical engineering

Phase-locked loop

IEEE Transactions on Circuits & Systems II Express Briefs

This brief presents a hybrid PLL by leveraging the advantages of analog and digital techniques in the frequency-control loop to achieve ultra-compact area and ultra-low power consumption simultaneously. Specifically, the hybrid loop consists of two paths: an integral path features a charge-sharing integrator realized by switched capacitors with high precision in digital discrete integration to improve the frequency resolution without deteriorating the output phase noise, and a proportional path directly switches the bias voltage of the VCO varactors to compensate the phase margin without costing extra power and area. Both paths are digitally controlled by a tiny power-efficient 1-bit bang-bang phase detector (BBPD). Prototyped in 28-nm CMOS, the 1.3-to-2.3-GHz PLL occupies a core area of 600 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}~^{2}$ </tex-math></inline-formula> and dissipates 380 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at a 0.8-V supply, of which only 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> is due to the hybrid loop. At a 2.0-GHz output, the PLL exhibits a reference spur of −60.5 dBc and a jitter of 1.71 ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> , resulting in state-of-the-art FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</sub> of −239.5 dB, and FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NRA</sub> of −271.7 dB.

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS