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doi.org/10.1016/j.compeleceng.2021.107200
A high-speed and scalable XOR-XNOR-based hybrid full adder design
Mehedi Hasan
22
,
Md. Shahbaz Hussain
1
,
...,
Sharnali Islam
17
View all 6 authors
Computers & Electrical Engineering
4.90
Volume: 93, Pages: 107200 - 107200
Published
: May 21, 2021
34
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Basic Info
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Paper Fields
Serial binary adder
Physics
Logic gate
Performance improvement
CMOS
Algorithm
NAND gate
Engineering
Adder
Power (physics)
Operations management
Electronic engineering
Computer science
XNOR gate
Quantum mechanics
Swing
Computer hardware
Carry-save adder
Scalability
Database
Mechanical engineering
Paper Details
Title
A high-speed and scalable XOR-XNOR-based hybrid full adder design
DOI
doi.org/10.1016/j.compeleceng.2021.107200
Published Date
May 21, 2021
Journal
Computers & Electrical Engineering
Volume
93
Pages
107200 - 107200
Notes
History
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