Cryptography

Public-key cryptography

Signature (topology)

Computer network

Mathematics

Hash function

Algorithm

Digital signature

Computer engineering

Computer architecture

Mathematical analysis

Parallel computing

Encryption

Embedded system

Elliptic curve cryptography

Implementation

Elliptic Curve Digital Signature Algorithm

Programming language

Digital Signature Algorithm

Geometry

Computer science

Side channel attack

Scheme (mathematics)

Computer security

Field-programmable gate array

Speedup

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

This article presents highly optimized implementations of the Ed25519 digital signature algorithm [Edwards curve digital signature algorithm (EdDSA)]. This algorithm significantly improves the execution time without sacrificing security, compared to exiting digital signature algorithms. Although EdDSA is employed in many widely used protocols, such as TLS and SSH, there appear to be extremely few hardware implementations that focus only on EdDSA. Hence, we propose two different field-programmable gate array (FPGA)-based EdDSA implementations, i.e., efficient and high-performance Ed25519 architectures applicable for a security level comparable to AES-128. Our proposed efficient Ed25519 scheme achieves an improvement of more than 84% compared to the best previous work by reducing the required area. It also incorporates more than 8× speedup. Furthermore, our proposed high-performance architecture shows a 21× speedup with more than 6200 digital signature algorithms per second, showing a significant improvement in terms of utilized area × time on a Xilinx Zynq-7020 FPGA. Finally, the effective side-channel countermeasures are embedded in our proposed designs, which also outperform the previous works.

Cryptographic Accelerators for Digital Signature Based on Ed25519