Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

Published on Jan 1, 2009
Estimated H-index: 1
Estimated H-index: 1
+ 5 AuthorsGang1
Estimated H-index: 1
一个低力量、便宜的先进加密标准(AES ) 协处理器为 Zigbee system-on-a-chip (SoC ) 被建议设计。建议 AES 协处理器的费用和电源消费被优化 SubBytes/InvSubBytes 和 MixColumns/InvMixColumns 的体系结构更加减少,由资源分享的方法一起集成加密和解密过程,并且基于有限州的机器( FSM )和钟使用层次电源管理策略 gating ( CG )技术。把 m 基于 SMIC 0.18 互补金属氧化物半导体(互补金属氧化物半导体) 技术, AES 协处理器的规模仅仅是大约 10.5 kgate,相应电源消费是 69.1 W/MHz,和产量是 32 Mb/s,它为 Zigbee 合理、足够系统。与另外的图案相比,建议体系结构消费更少的电源和少数硬件资源,它对 Zigbee 系统和另外的便携式的设备导致。
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