Physics

Phase-locked loop

Clock signal

Aerospace engineering

Power consumption

Engineering

Jitter

Sampling (signal processing)

Power (physics)

Range (aeronautics)

Electronic engineering

Converters

Computer science

Quantum mechanics

Time-to-digital converter

Telecommunications

Detector

IEEE Transactions on Circuits and Systems I Regular Papers

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

Jitter-Power Trade-Offs in PLLs