Gene

Computer hardware

Algorithm

Random number generation

Jitter

Statistics

Embedded system

Robustness (evolution)

Randomness tests

Telecommunications

Biochemistry

Computer science

Software portability

Randomness

Mathematics

Chemistry

Programming language

Wireless

Throughput

Field-programmable gate array

IEEE Transactions on Circuits and Systems I Regular Papers

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure