Gene

Quantum mechanics

Engineering

Bandwidth (computing)

Robustness (evolution)

Telecommunications

Biochemistry

Computer science

Physics

Noise shaping

Electronic engineering

Figure of merit

Chemistry

CMOS

Delta-sigma modulation

Sigma

Computer vision

IEEE Journal of Solid-State Circuits

The emerging noise-shaping (NS) successive approximation (SAR) architecture is highly efficient and compact; however, the order and signal-to-noise ratio (SNR) of sub-MHz NS SAR ADCs are still lower than conventional sigma-delta ADCs. This work proposes a cascaded NS (CaNS) SAR architecture that increases system order and enables more effective NS for higher SNR. The proposed architecture enhances the robustness of high-order NS performance at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the efficiency of residue amplification without sacrificing robustness. A prototype CaNS SAR ADC, fabricated in 28-nm CMOS, occupies 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 120 μW. The measured Signal to Noise and Distortion Ratio (SNDR) over 100-kHz bandwidth is 88 dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB.

A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension