Electrical engineering

Comparator applications

Chip

CMOS

Noise (video)

Image (mathematics)

Spurious-free dynamic range

Figure of merit

Preamplifier

Engineering

Comparator

Integral nonlinearity

Voltage

Artificial intelligence

Amplifier

Flash ADC

Effective number of bits

Materials science

Electronic engineering

Analog-to-digital converter

Converters

Computer science

Optoelectronics

Successive approximation ADC

Differential nonlinearity

IEEE Transactions on Biomedical Circuits and Systems

This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

A 0.3V 10b 3MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications