Electrical engineering

Physics

Channel (broadcasting)

Bandwidth (computing)

CMOS

Capacitor

Nyquist frequency

Inverter

Optics

Inductor

Engineering

Voltage

Attenuation

Programming language

Capacitive sensing

Electronic engineering

SIGNAL (programming language)

Computer science

Nyquist–Shannon sampling theorem

Telecommunications

This design presents a 56-Gb/s PAM4 CTLE in 40-nm CMOS. By adopting capacitive degeneration, inductive peaking, and inverter-based TIA, the two-stage CTLE generates a high-frequency peak which can compensate the gain attenuation due to channel loss at required Nyquist frequency. Through tuning the source degenerated capacitor of the first-stage gm-cell and the feedback inductor of the second-stage inverter-based TIA, the designed CTLE can achieve an 8.6-dB tuning range at the fixed peaking frequency of 22 GHz. The proposed structure reaches a DC-gain at — 0.6 dB from a 1-V voltage supply, which can recover the eye diagram of the 56-Gb/s PAM4 signal from distortion due to the 8.6-dB channel loss at Nyquist frequency.

A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixed Peaking Frequency in 40-nm CMOS