Modular design

Floating-point unit

Cache

Electrical engineering

Mathematics

Mobile technology

Operating system

Statistics

Microarchitecture

Computer architecture

Engineering

Mobile processor

Parallel computing

Embedded system

CPU cache

Mobile device

Efficient energy use

Computer science

Flexibility (engineering)

Multi-core processor

Floating point

Computer hardware

Scalability

Mobile Web

Workstation

IEEE Micro

The “Zen 2” processor is designed to meet the needs of diverse markets spanning server, desktop, mobile, and workstation. The core delivers significant performance and energy-efficiency improvements over “Zen” by microarchitectural changes including a new TAGE branch predictor, a double-size op cache, and a double-width floating-point unit. Building upon the core design, a modular chiplet approach provides flexibility and scalability up to 64 cores per socket with a total of 256 MB of L3 cache.

The AMD “Zen 2” Processor