Gene

Single event upset

Quantum mechanics

Computer hardware

Voltage

Engineering

Statistics

Embedded system

Node (physics)

Robustness (evolution)

Literature

Biochemistry

Parallel computing

Computer science

Mechanical engineering

Upset

Transistor

Physics

Mathematics

Static random-access memory

Structural engineering

Chemistry

Topology (electrical circuits)

Dual (grammatical number)

Electrical engineering

IEEE Transactions on Circuits and Systems I Regular Papers

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs