nanocomposite

easm

co mu

hypothermic

ch nh

forest_80181

freshwater_109897

accelerometer data

IEEE Journal of Solid-State Circuits

An ultra-low-power (ULP) capacitive microelectromechanical systems (MEMS) accelerometer analog front-end (AFE) chip with 290-μg/√Hz noise floor and 252-nW power consumption is presented. To achieve such low-noise characteristics under ULP operation, the proposed AFE utilizes a novel circuitry scheme, namely, feedforward noise reduction technique (FNRT), which cancels some of the correlated noise. The FNRT is a simple modification of the conventional self-balancing bridge (SBB) architecture without using any extra power and it can relax the noise requirement on amplifiers in AFE, thereby reducing its power consumption. The designed system uses an SAR ADC employing a simple signal-to-noise ratio (SNR) enhancement technique and includes a finite state machine (FSM) to enable dynamic configuration and duty-cycling operation. The AFE chip is implemented in a 0.18-μm complementary metal-oxide-semiconductor (CMOS) process and achieves a dynamic range of 65 dB and the bias instability of 62.8 μg.

A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications