Reconfigurable computing

Control reconfiguration

Embedded system

Scheduling (production processes)

Operating system

Economics

Parallel computing

Computer science

Visual arts

Architecture

Hardware acceleration

Software

Computer architecture

Task (project management)

Management

Design space exploration

Processor scheduling

Operations management

Reconfigurability

Schedule

Application-specific integrated circuit

Field-programmable gate array

Hardware architecture

Symmetric multiprocessor system

IEEE Access

Real-time performance is the primary requirement for edge computing systems.However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent.As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention.The type of accelerators determines the performance of the edge computing system largely.The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA).FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios.Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs.Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency.This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform.We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency.We conduct a set of experiments on the Zynq platform to verify the proposed framework.Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.

A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing