Electrical engineering

Channel (broadcasting)

Chip

Transistor

Phase-shift keying

Bit error rate

Engineering

Voltage

Demodulation

Electronic engineering

Computer science

BiCMOS

Radio frequency

IEEE Journal of Solid-State Circuits

This paper presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB were measured. A data rate of 36 Gb/s was wirelessly measured at 30-cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 × 3.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area, including PADs and test circuits (2.5-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area), and consumes a total dc power of 200.25 mW.

A 115–135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method