Logic gate

Lock (firearm)

Block (permutation group theory)

Logic block

Computer network

Mathematics

Algorithm

Engineering

Embedded system

Set (abstract data type)

Programming language

Geometry

Computer science

Routing (electronic design automation)

Field-programmable gate array

Mechanical engineering

In this paper, we propose a novel and SAT-resistant logic-locking technique, denoted as Full-Lock, to obfuscate and protect the hardware against threats including IP-piracy and reverse-engineering. The Full-Lock is constructed using a set of small-size fully Programmable Logic and Routing block (PLR) networks. The PLRs are SAT-hard instances with reasonable power, performance and area overheads which are used to obfuscate (1) the routing of a group of selected wires and (2) the logic of the gates leading and proceeding the selected wires. The Full-Lock resists removal attacks and breaks a SAT attack by significantly increasing the complexity of each SAT iteration.

Full-Lock