Ring oscillator

Electrical engineering

Bandwidth (computing)

CMOS

Capacitor

Voltage-controlled oscillator

Integrator

Noise shaping

Engineering

Voltage

Effective number of bits

Electronic engineering

Analog-to-digital converter

Computer science

Delta-sigma modulation

Successive approximation ADC

Telecommunications

IEEE Transactions on Circuits and Systems I Regular Papers

A continuous-time second-order ΔΣ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.

Highly Digital Second-Order $\Delta\Sigma$ VCO ADC