power amplifier

nm cmos

frequency synthesizer

gain db

cmos process

IEEE Microwave and Wireless Components Letters

A variable-gain low-noise amplifier implemented in a 65-nm CMOS process for a beamforming front-end chip is presented, of which the phase remains constant during gain variations. The phase compensation characteristic is achieved by introducing a shunt PMOS and a parallel resistor at the differential outputs of common-gate (CG) transistors. This allows the gain to be controlled without phase variation by adjustment of the combined gate voltage of the CG transistor and the shunt PMOS at the same time. The proposed device shows a gain of 20.8 dB and a noise figure of 3.71 dB at 31 GHz. It shows a root-mean-square phase error of less than 3° over the gain control range of 10.6 dB at 30-34.5 GHz.

A Ka-Band Phase-Compensated Variable-Gain CMOS Low-Noise Amplifier