Study on 4H-SiC GGNMOS Based ESD Protection Circuit With Low Trigger Voltage Using Gate-Body Floating Technique for 70-V Applications
Paper Details
Title
Study on 4H-SiC GGNMOS Based ESD Protection Circuit With Low Trigger Voltage Using Gate-Body Floating Technique for 70-V Applications
Published Date
Dec 11, 2018
Journal
Volume
40
Issue
2
Pages
283 - 286
Notes
History