architecture

sar adc

IEEE Journal of Solid-state Circuits

This paper demonstrates a multi-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) architecture for low-power and high-speed operation. The proposed dual reference shifting and interpolation technique reduces the power and area overhead of the multi-bit/ cycle SAR architecture, allowing for a higher number of bit quantization for each conversion cycle and thus, a higher conversion rate. To prove the concept, a 12-bit 32-way time-interleaved 4-b/cycle SAR ADC prototype is fabricated in 65-nm CMOS technology. The ADC prototype can be configured with multiple sampling rates (1.6, 3.2, and 6.4 GS/s). It measures a peak effective number of bits (ENOB) of 10.9 bits at 6.4 GS/s and 9.4 ENOB at the maximum input frequency of 1 GHz. The prototype achieves a Schreier figure-of-merit (FOMSchreier) of 154.9 dB at 6.4-GS/s sampling rate.

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation