Quantum mechanics

Computer hardware

Voltage

Engineering

Capacitance

Bit (key)

Statistics

Materials science

Computer security

Successive approximation ADC

Telecommunications

Calibration

Computer science

Capacitor

Physics

Mathematics

Spurious-free dynamic range

Electronic engineering

Spurious relationship

Electrode

Chip

12-bit

CMOS

Optoelectronics

Machine learning

Dynamic range

Electrical engineering

IEEE Journal of Solid-State Circuits

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS