Voltage

Engineering

Jitter

PLL multibit

Telecommunications

Computer science

BiCMOS

Frequency synthesizer

Phase noise

Transistor

Physics

Wideband

Direct digital synthesizer

Electronic engineering

Orthogonal frequency-division multiplexing

Baseband

Frequency offset

Voltage-controlled oscillator

Channel (broadcasting)

Wireless

CMOS

Frequency multiplier

Electrical engineering

Phase-locked loop

The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7 GHz-11.8 GHz PLL using only one VCO is followed by a frequency sixtupler composed of a tripler and a doubler. The measured phase noise at 1 MHz offset from the 10 GHz PLL output frequency is below -108 dBc/Hz. For a 60 GHz OFDM system, this corresponds to an rms phase error of 1.5° and a PLL rms jitter of 70 fs after common phase error correction. The synthesizer chip occupies a chip area of 3.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws 144 mA from a 3.3 V supply.

Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler