Transmitter

Engineering

Noise figure

Telecommunications

Amplifier

Computer science

Antenna (radio)

Phase noise

Balun

Low-noise amplifier

Radio receiver design

Image (mathematics)

Electronic engineering

Artificial intelligence

Channel (broadcasting)

Chip

Wireless

Noise (video)

CMOS

Electrical engineering

IEEE Microwave and Wireless Components Letters

This work demonstrates a fully integrated 24 GHz CMOS receiver targeted for low power and compact wireless sensor nodes utilizing FMCW radar for wireless local positioning. The receiver incorporates a highly integrated low noise amplifier, passive mixer and on-chip transformer balun for single-to-differential conversion of LO. The receiver chip has been realized in a 130 nm CMOS technology. At 24 GHz RF the measured receiver performance includes a power conversion gain of 16.5 dB, a noise figure of 5.3 dB, an input power at 1 dB compression point of -26 dBm and an IIP3 of -15 dBm. The complete receiver chip consumes 18 mW from a 1.2 V power supply with 13 mW for the LNA and 5 mW for the output IF buffer. The chip area is 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The realized receiver compares the best 24 GHz CMOS receiver realizations published so far.

Low Noise 24 GHz CMOS Receiver for FMCW Based Wireless Local Positioning