Electrical engineering

Chip

CMOS

Electronic circuit

Macroeconomics

Frequency multiplier

Multiplier (economics)

Engineering

Voltage

Dropout voltage

Economics

Electrical impedance

Electronic engineering

Integrated circuit

Output impedance

Voltage divider

Voltage multiplier

IEEE Journal of Solid-State Circuits

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique