Finite impulse response

Computer network

Header

Algorithm

Filter (signal processing)

Digital signal processor

Half-band filter

Embedded system

Filter design

Digital filter

VHDL

Computer science

Digital signal processing

Computer hardware

Computer vision

Field-programmable gate array

Root-raised-cosine filter

Results in Engineering

The objective of this project is to make a detailed study on the Hardware architectures of DSP and FPGA then to carry out a comparison between the two platforms in order to achieve a better implementation while keeping to increase the performances and obtain a better signal processing quality. For this raison, we wanted to make a digital FIR filter of 40 order bandpass and a symmetrical parallel architecture of this FIR filter. Matlab's FDATOOL is used to design this filter. This tool allows us to generate the VHDL code of the filter to implement it on Altera Cyclone III FPGA which is placed on the Texas Instruments TSW6011 board, this tool also allows us to generate all the coefficients of our filter in a header file C in order to use them in a program of the FIR filter written in C which will then be loaded on the DSP TMS320C6713. This achievement allows us to distinguish between different hardware architectures and make a comparison in terms of execution speed and power consumption.

Comparison study of hardware architectures performance between FPGA and DSP processors for implementing digital signal processing algorithms: Application of FIR digital filter