Surface roughness

Work function

Electrical engineering

Engineering

Logic gate

Composite material

Enhanced Data Rates for GSM Evolution

Voltage

Nanotechnology

Transistor

Materials science

Gate oxide

Electronic engineering

Layer (electronics)

Computer science

Optoelectronics

Metal gate

Nanosheet

Surface finish

Telecommunications

Process variation

IEEE Transactions on Electron Devices

In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) induced by process fluctuations are investigated for the first time. Four process variability sources including work-function variation (WFV), line edge roughness (LER), gate edge roughness (GER), and random dopant fluctuation (RDF) are characterized. Compared to the conventional NA GAA FET, the differences mainly exist in GER. The electrostatic potential variation induced by GER in CFET is affected by both the common metal gate and the additional p-type work-function (p-WF) liner for p-FET. Therefore, the impact of GER on p-FET is much larger than n-FET as well as conventional NS GAA FET. Thickening the p-WF liner is proposed to overcome the drawback. Calculated overall variations considering all process fluctuation sources are also discussed, highlighting the impact of the dual-WF gate on p-FET. The results are helpful for the characterization and optimization of variations in CFET and precise CFET-based circuit design.

Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)