Graph

Engineering design process

Design flow

Data-flow analysis

Computer architecture

Engineering

Embedded system

Physical design

Circuit design

Computer science

Data flow diagram

Electronic design automation

Routing (electronic design automation)

Integrated circuit design

Theoretical computer science

Scalability

Database

Mechanical engineering

ACM Transactions on Design Automation of Electronic Systems

Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks (GNNs) are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate Register Transfer Levels, and netlists. In this article, we present a comprehensive review of the existing works linking the EDA flow for chip design and GNNs. We map those works to a design pipeline by defining graphs, tasks, and model types. Furthermore, we analyze their practical implications and outcomes. We conclude by summarizing challenges faced when applying GNNs within the EDA design flow.

A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications