Electrical engineering

Physics

Interconnection

Meteorology

Chip

Flip chip

Chip-scale package

Engineering

Junction temperature

Composite material

Integrated circuit packaging

Materials science

Thermal

Electronic engineering

Layer (electronics)

Adhesive

Telecommunications

Mechanical engineering

IEEE Transactions on Components Packaging and Manufacturing Technology

Heterogeneous integration technology makes possible the integration of multiple separately manufactured components into a single higher level assembly with enhanced functionality and improved operating characteristics. Various types of advanced heterogeneous packages are available, including 2.5-D integrated circuit (IC), fan-out chip on substrate (FOCoS) chip-first, and FOCoS chip-last. This study constructs a nonlinear simulation technique (3-D simulation model) to explore the warpage, extreme low-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> (ELK) interconnect stress, redistribution layer (RDL) trace stress, and board-level solder joint reliability of all three packages. The validity of the simulation model is confirmed by comparing the numerical results for the in-plane dimensional change of an FOCoS chip-last package with the experimental observations over the temperature range of 30 &#x00B0;C&#x2013;260 &#x00B0;C. The thermal performance (i.e., junction-to-ambient thermal resistance) of the three packages is then examined and compared. Finally, <inline-formula> <tex-math notation="LaTeX">$2^{5}$ </tex-math></inline-formula> factorial designs with the analysis of variance (ANOVA) are conducted to examine the effects of the main structural design parameters of the FOCoS chip-last package on its thermomechanical reliability under typical thermal loading conditions. It is shown that a thinner polyimide (PI) layer is beneficial in improving the package reliability by minimizing the coefficient of temperature expansion (CTE) mismatch between the PI layer and the RDL trace, respectively.

Thermal and Mechanical Characterization of 2.5-D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages