Deep learning

Pure mathematics

Mathematics

Operating system

Computer engineering

Computer architecture

Machine learning

Edge device

Parallel computing

Embedded system

Artificial intelligence

Applications of artificial intelligence

Reconfigurability

Computer science

Cloud computing

Dataflow

Field (mathematics)

Process (computing)

Deep neural networks

Artificial neural network

Telecommunications

Convolutional neural network

Future Internet

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks