Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Volume: 47, Issue: 2, Pages: 153 - 163
Published: Jun 8, 2021
Abstract
The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm...
Paper Details
Title
Design and implementation of power and area optimized AES architecture on FPGA for IoT application
Published Date
Jun 8, 2021
Volume
47
Issue
2
Pages
153 - 163
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