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doi.org/10.1109/tcsii.2019.2940558
Original paper
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation
Mehedi Hasan
13
,
Md. Jobayer Hossein
3
,
Md. Shadman Mostafa
15
IEEE Transactions on Circuits & Systems II Express Briefs
4.90
Published
: Aug 1, 2020
98
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Paper Details
Title
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation
DOI
doi.org/10.1109/tcsii.2019.2940558
Published Date
Aug 1, 2020
Journal
IEEE Transactions on Circuits & Systems II Express Briefs
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