Floating-point unit

IEEE floating point

Mathematics

Operating system

Algorithm

Unit (ring theory)

Single-precision floating-point format

Mathematics education

Philosophy

Parallel computing

Artificial intelligence

Exponent

Overhead (engineering)

Computer science

Linguistics

Floating point

Computer hardware

16-bit

Binary number

Artificial neural network

Control unit

Arithmetic

IEEE Transactions on Computers

In this paper, a new flexible multiple-precision multiply-accumulate (MAC) unit is proposed for deep neural network training and inference. The proposed MAC unit supports both fixed-point operations and floating-point operations. For floating-point format, the proposed unit supports one 16-bit MAC operation or sum of two 8-bit multiplications plus a 16-bit addend. To make the proposed MAC unit more versatile, the bit-width of exponent and mantissa can be flexibly exchanged. By setting the bit-width of exponent to zero, the proposed MAC unit also supports fixed-point operations. For fixed-point format, the proposed unit supports one 16-bit MAC or sum of two 8-bit multiplications plus a 16-bit addend. Moreover, the proposed unit can be further divided to support sum of four 4-bit multiplications plus a 16-bit addend. At the lowest precision, the proposed MAC unit supports accumulating of eight 1-bit logic AND operations to enable the support of binary neural networks. Compared to the standard 16-bit half-precision MAC unit, the proposed MAC unit provides more flexibility with only 21.8 percent area overhead. Compared to a standard 32-bit single-precision MAC unit, the proposed MAC unit requires much less hardware cost but still provides 8-bit exponent in the numerical format to maintain large dynamic range for deep learning computing.

New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference