nm cmos

IEEE Journal of Solid-state Circuits

In this paper, a transimpedance amplifier (TIA) is presented that utilizes a modified pseudo-resistor (PR) with improved robustness against temperature and process variations, enhanced linearity, and reduced parasitics. Using a biasing scheme named pseudo current mirror, the conventional dependence on absolute process parameters is reduced to a dependence on matching of alike devices. The linearity and noise performance as well as the immunity against process variations of the presented TIA are improved by the series connection of multiple PR elements. Moreover, it is shown how implementing the design in a silicon-on-insulator (SOI) technology reduces critical parasitics, which in turn enables the use of the multi-element PR in highspeed, high-gain, and low-distortion TIAs. A prototype realization in a 180-nm CMOS SOI technology achieves a tunability in transimpedance of three orders of magnitude from 1 GΩ down to 1 MΩ with corresponding bandwidths from 8 kHz to 2 MHz. By design, the contribution of shot noise is rendered negligible and the white noise floor of the prototype realization approaches the theoretical thermal noise limit, e.g., 5.5 fA/√(Hz) for a transimpedance of 1 GΩ and 140 fA/√(Hz) for 1 MΩ. Total Hz for a harmonic distortion values of less than 0.1% are achieved for an input amplitude of 300 pA p-p for 1 GΩ, 4.0 nA p-p for 100 MΩ, and 40 nA p-p for 10 MΩ, and less than 1% is achieved for an input amplitude of 550 nA p-p for 1 MΩ. The presented TIA consumes an area of 0.07 mm 2 and dissipates a power o...

A 0.1% THD, 1-M $\Omega$ to 1-G $\Omega$ Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor