Register optimizations for stencils on GPUs
Published: Feb 10, 2018
Abstract
The recent advent of compute-intensive GPU architecture has allowed application developers to explore high-order 3D stencils for better computational accuracy. A common optimization strategy for such stencils is to expose sufficient data reuse by means such as loop unrolling, with the expectation of register-level reuse. However, the resulting code is often highly constrained by register pressure. While current state-of-the-art register...
Paper Details
Title
Register optimizations for stencils on GPUs
Published Date
Feb 10, 2018
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