Improved StrongARM latch comparator: Design, analysis and performance evaluation
Published: Jun 1, 2017
Abstract
This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced...
Paper Details
Title
Improved StrongARM latch comparator: Design, analysis and performance evaluation
Published Date
Jun 1, 2017
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