The microarchitecture of the IBM eServer z900 processor

Volume: 46, Issue: 4, Pages: 381 - 395
Published: Jul 1, 2002
Abstract
The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64- bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target...
Paper Details
Title
The microarchitecture of the IBM eServer z900 processor
Published Date
Jul 1, 2002
Volume
46
Issue
4
Pages
381 - 395
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